Domain-specific and reconfigurable instruction cells based architectures for low-power SoC

Silicon technologies have been conforming to the maxim of Moore's law for the past 40 years [131], but, even though production prices per unit have gone down, the NRE costs for making new chips keep going up with every new technology. This made a number of applicationsectors discouraged to design new chips and in favour of adopting more generic solutions such as FPGAs and high-performance DSPs. These two programmable technologies have also evolved dramatically over the past decade providing much larger usable silicon areas and higher throughputs at the expense of increased power consumptions. New communication standards and the requirements of modem mobile-device's users push the silicon towards processing more data in an increasingly shorter time; this is precisely the case for new compression formats targeting high-quality low-bandwidth multimedia. This presses forward the need for new programmable hardware solutions that intrinsically achieve generality, high-performance and, most importantly, low power consumption. This work investigates the design of reconfigurable hardware architectures to address these issues. Two novel solutions are thus proposed along with the implementations of several multimedia applications on them; the first architecture fits as a middle ground between FPGAs and ASICs in terms of performance and cost. This is achieved by using coarse-grain functional units combined with programmable interconnects to build flexible, highperformance and low-power circuits. A framework for generating and programming the custom domain-specific reconfigurable arrays is also proposed. The tool-flow leverages some of the design effort that goes in creating and using the arrays by facilitating the reuse of previous design elements. Furthermore, this work proposes novel direction-aware routing elements to allow efficient tailoring of interconnect structures to the application. The second proposed processing architecture adds the dimension of high-level programmability to the reconfigurable arrays. This is achieved by using functional units that can be directly matched to elements in a compiler's internal representation of software. By using a custom instruction-controller the array can execute control operations in a similar way to processors, while at the same time allowing highly efficient mapping of datapath circuits. Coupled to the low-power and high-throughput achieved, this creates a viable alternative to FPGAs, DSPs and ASICs suitable for deployment in high performance mobile applications entirely programmable using languages such as C/C++.